NBTI defects in SiO2: identification and low thermal budget annealing strategies for future CMOS technology architectures
Abstract: Future CMOS technology architectures (Nanosheets, CFETs, Sequential 3D tier stacking) will require the development of low thermal budget process modules, including gate stack. A high-quality SiO2 interfacial layer, obtained in existing technologies by high-temperature (≥850°C) oxidation or annealing, is crucial for pMOS NBTI reliability. In low temperature SiO2, unrelaxed interface strain induces large defect densities, which we have identified – based on their electrical signature as compared to ab-initio calculations – as hydroxyl-E’ structures forming at stretched Si-O bonds. Based on theoretical insights, we have developed a combination of atomic and molecular hydrogen treatments to passivate these oxide defects efficiently at low temperatures (100-400°C), yielding an SiO2 quality which outperforms a reference thermal oxide grown at 900°C and a contemporary Replacement Gate (RMG) stack exposed to a conventional high-temperature anneal. We elucidate the implications of hydroxyl-E’ defect de-activation by hydrogen on the permittivity of the SiO2 interfacial layer, on its effectiveness as a tunneling barrier and on the carrier mobility in the underlying Si channel, beside the dramatic improvement in NBTI reliability. Finally, we demonstrate that this low temperature oxide defect passivation is sufficiently thermally stable to withstand Back-End-Of-Line processing in a complete CMOS IC fabrication flow.
Jacopo Franco is a Principal Member of Technical Staff in the Reliability group of the Advanced Reliability, Robustness and Test department of imec, Belgium. He received the B.Sc. (2005) and M.Sc. (2008) from the University of Calabria – Italy, and the Ph.D. degree from KU Leuven – Belgium (2013) in Electrical Engineering. His research focuses on CMOS FEOL reliability characterization, optimization, and modelling, and in particular: i) on gate stack development for novel device technologies (SiGe, Ge, III-V, IGZO), architectures (finFETs, FD-SOI, Nanowires, Nanosheets), and integration schemes (Sequential 3D tier stacking, CFETs); ii) on characterization and physics-based modelling of FEOL degradation mechanisms (BTI, Hot Carrier, Off-state degradation, TDDB, RTN, time-dependent variability); iii) on reliability compact models to accurately propagate individual device aging to circuit level. He has (co-)authored 250+ contributed or invited papers and 3 patent families, and he is a recipient of several IEEE awards: Best Student Paper at SISC (2009), EDS Ph.D. Student Fellowship (2012), Paul Rappaport Award (2011), Best (2012), Outstanding (2014), and Best Student (2016) paper awards at IRPS. He has been serving in various functions on the Technical Program Committees of IRPS (Chair of the ‘XT-Transistors’ subcommittee in 2020), SISC, IIRW, ESREF, WoDiM and InFOS conferences, and as an Editor of IEEE Transactions on Device and Materials Reliability (2017-2020) and of IEEE Transactions on Electron Devices (2020-).