Frontiers in the atomistic simulation of nanoscale electron devices
Abstract: Addressing accurate simulations of electronic and transport properties of nanoscale devices requires to consider physical models including quantum mechanical effects as well as phonon scattering and spatial fluctuations due to non-ideal surfaces and defects. Self-consistent quantum simulations based on the non-equilibrium Green’s function formalism have been extensively used for this purpose during the last years. This talk will briefly discuss this methodology and show advantages and drawbacks of different Hamiltonian models used to describe the energy dispersion of the channel material, going from the effective mass approximation to the empirical tight-binding model. Illustrative results on FDSOI and nanowire FETs will be presented. Finally, the theory and application of a ﬁrst-principles transport methodology employing a basis set composed of the Bloch functions will be introduced. Such an approach enables full ab-initio quantum transport calculations with a reasonable computational cost and permits to address self-consistent simulations of electron devices based on novel 2D materials.
Marco Pala received the physics degree and the PhD in electronical engineering from the University of Pisa, Italy in 2000 and 2004, respectively. From 2004 to 2005 he was post-doc at CEA-LETI, Grenoble, France. He joined the CNRS as research scientist in 11/2005 at IMEP-LAHC, Grenoble. From 2016 he is with the Centre for Nanoscience and Nanotechnology (C2N), Palaiseau, France, where is the leader of the computational electronics group. His main research interests concern the electronic and transport properties of nanoscale devices. Recently, he worked on quantum transport calculations based on ab-initio methods to assess the use of new materials in nanoelectronics. He is co-author of 73 papers in peer-reviewed journals and 48 proceedings in international conferences.
Modeling Advances for Single Photon Avalanche Diode: From optical simulation to Monte Carlo simulation.
Abstract: Single Photon Avalanche Diodes (SPAD) are key optoelectronic detectors for medical imaging, camera ranging and automotive laser imaging detection and ranging (LiDAR) applications. The optimization of the SPAD Figure Of Merits is strategic at an industrial level. Currently, the Photon Detection Probability (PDE), the timing statistic response to avalanche (Jitter) and the SPAD quench probability must be co-optimized using advanced numerical methods.
In this presentation we report a rigorous simulations using Monte Carlo Breakdown Probability (BRP) predictions coupled to optical simulations of PDE and Jitter (see figure 1). We also discuss in detail, the quench probability of these diodes once in avalanche. This latter point, rarely discussed in literature, is addressed using a Mixed-Mode Monte Carlo approach including the quench circuit.
Denis Rideau received a Ph.D. degree in Physics from the University of Orsay, France in 2001, and an Engineering degree at ESIEE, Paris in 1996. He is now performing TCAD simulations at STMicroelectronics, Crolles in France. His research interests are modelling and simulation of semiconductor nanodevices, with emphasis on quantum effects, strain effects, wafer orientations, and alternative channel materials in FDSOI and FinFets. He has developed several codes for computing the electronic bandstructures in strain Si, Ge, and SiGe devices using the k.p-Schrödinger approach. He investigates by means of TCAD simulations advanced devices, including alternative III-V channel materials. In parallel he developed advanced solvers (Monte Carlo and NEGF) to simulate the transport properties of single-gate and multi-gate devices featuring stress, substrate orientation, SiGe materials and high-k/metal gate. He is an expert in the calibration of industrial TCAD software aiming in providing parameters but also validation and benchmarking on experimental.
Ferroelectric Tunnel Junction memristors for neuromorphic technologies
Abstract: Ferroelectric Tunnel Junction (FTJ) memristors show promise as electronic synapses for low power neuromorphic circuits. First, the progress will be reviewed in the field of perovskite and recently discovered Hafnia based ferroelectrics such as Hf0.5Zr0.5O2 (HZO), considering both double and single- layer gate stack designs. Then, the focus will shift on Metal-Ferroelectric-Semiconductor (MFS)-FTJs where the bottom electrode is a semiconductor (Ge or Nb:STO) and the top is W or TiN metal. The metastability of ferroelectricity due to depolarization fields will be discussed and the lower limits of HZO thickness to obtain stable ferroelectricity will be determined. It will be shown that HZO based MFS-FTJ behave as analog memristive non-volatile memories with very good endurance and retention and with a number of intermediate states showing synaptic plasticity, that is long term potentiation and depression as a function of the number of sequential pulses of varying amplitude or width. The role in the FTJ switching behavior of the Schottky barrier near the semiconductor/HZO interface will be elucidated. The programming and reading voltage of the synaptic devices are below 1V which makes them suitable for ultra-low power in-memory neuromorphic computing. Performance characteristics determining speed and low power operation of neuromorphic circuits will be addressed. Integration with CMOS either in the FEOL or the BEOL will also be discussed.
Dr. Athanasios Dimoulas is Research Director at NCSR-DEMOKRITOS in Athens. He is founder and head of Epitaxy and Surface Science Laboratory (ESSL) of the Institute of Nanoscience and Nanotechnology since 1999 and currently member of the advisor committee for physical sciences of the Greek government. He has been EC Human Capital and Mobility fellow at the university of Groningen, post-doctoral fellow at CALTECH and Research Associate at the University of Maryland. He has been visiting research scientist at IBM-Zurich and he has been appointed as Chair of Excellence at CEA-INAC(IRIG), and U. Grenoble Alpes, France. He has coordinated several collaborative EU projects and has been awarded the ERC advanced and proof of concept grants. He has served as chair of INFOS and chair of TPC committees of ESSDERC and IEDM. His current interests include 2D materials, topological materials and Hafnia based ferroelectric memristors for neuromorphic computing technologies.
NBTI defects in SiO2: identification and low thermal budget annealing strategies for future CMOS technology architectures
Abstract: Future CMOS technology architectures (Nanosheets, CFETs, Sequential 3D tier stacking) will require the development of low thermal budget process modules, including gate stack. A high-quality SiO2 interfacial layer, obtained in existing technologies by high-temperature (≥850°C) oxidation or annealing, is crucial for pMOS NBTI reliability. In low temperature SiO2, unrelaxed interface strain induces large defect densities, which we have identified – based on their electrical signature as compared to ab-initio calculations – as hydroxyl-E’ structures forming at stretched Si-O bonds. Based on theoretical insights, we have developed a combination of atomic and molecular hydrogen treatments to passivate these oxide defects efficiently at low temperatures (100-400°C), yielding an SiO2 quality which outperforms a reference thermal oxide grown at 900°C and a contemporary Replacement Gate (RMG) stack exposed to a conventional high-temperature anneal. We elucidate the implications of hydroxyl-E’ defect de-activation by hydrogen on the permittivity of the SiO2 interfacial layer, on its effectiveness as a tunneling barrier and on the carrier mobility in the underlying Si channel, beside the dramatic improvement in NBTI reliability. Finally, we demonstrate that this low temperature oxide defect passivation is sufficiently thermally stable to withstand Back-End-Of-Line processing in a complete CMOS IC fabrication flow.
Jacopo Franco is a Principal Member of Technical Staff in the Reliability group of the Advanced Reliability, Robustness and Test department of imec, Belgium. He received the B.Sc. (2005) and M.Sc. (2008) from the University of Calabria - Italy, and the Ph.D. degree from KU Leuven - Belgium (2013) in Electrical Engineering. His research focuses on CMOS FEOL reliability characterization, optimization, and modelling, and in particular: i) on gate stack development for novel device technologies (SiGe, Ge, III-V, IGZO), architectures (finFETs, FD-SOI, Nanowires, Nanosheets), and integration schemes (Sequential 3D tier stacking, CFETs); ii) on characterization and physics-based modelling of FEOL degradation mechanisms (BTI, Hot Carrier, Off-state degradation, TDDB, RTN, time-dependent variability); iii) on reliability compact models to accurately propagate individual device aging to circuit level. He has (co-)authored 250+ contributed or invited papers and 3 patent families, and he is a recipient of several IEEE awards: Best Student Paper at SISC (2009), EDS Ph.D. Student Fellowship (2012), Paul Rappaport Award (2011), Best (2012), Outstanding (2014), and Best Student (2016) paper awards at IRPS. He has been serving in various functions on the Technical Program Committees of IRPS (Chair of the ‘XT-Transistors’ subcommittee in 2020), SISC, IIRW, ESREF, WoDiM and InFOS conferences, and as an Editor of IEEE Transactions on Device and Materials Reliability (2017-2020) and of IEEE Transactions on Electron Devices (2020-).
GaN at Infineon: A ten year’s journey to develop high performance and reliable power devices
The development and industrialization of new semiconductor materials is a question of decades rather than years. At the moment we are privileged to witness the implementation of Gallium Nitride as game changing semiconductor for power devices. This presentation will depict the development journey from academic research to mature, high performing, and reliable GaN power technologies. After describing the promise and value proposition of the material system, leading edge device concepts will be presented. Unrivaled values for efficiency and power density have been demonstrated in a variety of power electronic applications. The presentation will also touch the cost efficient and stable manufacturing for both GaN base epitaxy as well as the complex and new GaN power device production processes. Moreover, market success strongly depends on device reliability, one of the major challenges researchers and industrial engineers have been trying to tackle over many years. The main reliability responses of normally-off GaN power HEMTs such as gate module reliability, time-dependent dielectric breakdown, and dynamic Rdson will be discussed. Finally, it will be shown that an outstanding R&D ecosystem involving several large-scale European funding projects as well as international partnerships have been key success factors in this exciting development journey.
Thomas Detzel received the M.S. degree in physics from the University of Constance, Germany, in 1991 and the Ph.D. degree in surface and thin-film physics in 1994 from the Max-Planck-Institute Garching, Germany. Afterwards he was a Postdoc with the Institut de Physique et Chimie des Matériaux de Strasbourg, France. In 1995, he was with Rodel Europe GmbH, where he was an Application Manager for chemical–mechanical polishing of semiconductor wafers. In 1999, he joined Infineon Technologies Austria AG in Villach, where he was responsible for the metallization development of automotive power semiconductors, has been the Project Manager of different power integrated circuit developments from 2004-2011, and has been leading the research project Robust Metallization and Interconnect at the Competence Center for Automotive and Industrial Electronics from 2006-2011. Since 2011 he has been managing the development group for GaN power technologies at Infineon Villach and is currently a Senior Director in Infineon’s GaN program.